Sample Projects

 

High-Speed Mixed-Signal IP Block

A current IC design project involves the design of a high-speed mixed-signal IP block for 1394 communications to at least S1600 level. The block performs the function of the PMD in the Firewire specification and, via a Serdes, provides a parallel communications interface to the higher level digital blocks.  The design interfaces directly to the copper serial bus, performs the clock recovery and character alignment and provides the facilities for bus negotiation. Targeted at a mainstream 0.13µ technology, the IP is intended for use/reuse by systems designers without specific process technology knowledge.

Image Processing System Design

The design team contributed embedded software and technology translation of Heriot-Watt University’s research outcomes to a major project with the medical devices company Optos PLC. The technology provided ensured correct alignment of a laser with a patient's eye to allow a scan to be performed. This software has now been incorporated into a new product line.

MEMS Pressure Sensor

The Institute has developed a pressure sensor suitable for application in a wide range of industrial and consumer products, using micro-electromechanical systems [MEMS] technology. The device is based on silicon MEMS and uses only materials and processes which are completely compatible with today’s CMOS electronics industry; which supplies the vast majority of electronics for the home and office.

Optimised MPEG Video Player

This project involves the development of a power-optimised MPEG player using a mixed hardware/software architecture guided by profiling the video decoding algorithm. The dedicated modular hardware interfaces via DMA to its host system over ARM's open standard AMBA AHB bus and is intended to be independent of the host processor. Complexity and power are further reduced through the use of pseudo-fixed-point arithmetic. Offloading the bulk of the decoding work to dedicated hardware enables a high frame rate to be achieved at modest clock rates using a processor of the scale of an ARM7. Initial implementation is FPGA-based though technology requirements for an ASIC implementation are not demanding.