Unit 1: Introduction to HDLs and Verilog

This unit begins by introducing the module and its aims. The reasons for using a Hardware Description Language (HDL) are discussed and general background information is given. The different levels at which an HDL can be employed are shown and clock-driven and event-driven simulators are briefly discussed. VHDL and Verilog are introduced and their origins, and some of their comparative advantages and disadvantages are considered.

Unit 2: Verilog Syntax and Examples

In the first part of this unit the Verilog module is introduced and the fact that a module represents blocks of hardware is emphasised. There follows a introduction to gate primitives and their ports before we see how a module can also be defined at a behavioural level. An example module is shown and simulated using the Altera software. Many students are familiar with the Altera/Xilinx FPGA design packages and we see how these implement only a restricted sub-set of the Verilog language and, not surprisingly, are very limited to FPGA system design.

The second part of this unit looks at basic Verilog syntax, including signal values, numbers, identifiers, nets, registers, buses/vectors, and modules and their ports. The two Verilog simulators used in this module, Verilogger Pro 6.5 (PC-based) and Cadence Verilog (available on UNIX machines in the ISLI), are introduced. The former is identified as the simulator of choice for this module, though it is emphasised that this simulator (which is a freely-available evaluation version) is limited and only suitable for learning the basics of Verilog. A full simulation example is given and the simulation sequence is explained.

Unit 3: Operators, Module Instantiation, Testbenches

This unit starts with the different kinds of operator that are available in Verilog and then moves on to examine the different kinds of delays and “waits” used in Verilog code. We then see how to instantiate modules, and some time is devoted to the merits of named port association as opposed to positional port association. Finally we start to explore the subject of test-benches and give some examples of how simple test-benches are created and simulated

Unit 4: Procedures and Procedural Statements

This unit is devoted to procedures and procedural statements. Therefore we go through initial, always, if and case statements, followed by an examination of the different kinds of loops available in Verilog. We then look at parameters and see how to over-ride them. Next blocking and non-blocking assignments are examined at some length and several examples are given. Finally tasks and functions are introduced and examples are given.

Unit 5: Compiler Directives, Finite State Machines, Synthesisability

This unit first introduces the main compiler directives but is mainly devoted to Finite-State Machines (FSMs) and considerations of synthesisability. Different kinds of FSM such as explicit/implicit forms are discussed and Verilog realisations of several examples are produced using if/else and case structures. A variety of practical points involved in the realisation of FSMs are also considered. We then move into a review of the sub-set of Verilog that is synthesisable, and this leads into the hand-optimisation and automatic optimisation of Verilog code. A discussion on simulation race hazards ensues and finally a number of points related to the readability, maintainability and portability of Verilog code are raised.

Unit 6: Introduction to VHDL and how it compares to Verilog

This unit is a very basic introduction to Verilog’s main competitor, VHDL. The basic structure of VHDL, and how it compares to that of Verilog, is discussed, and then the main VHDL statements and definitions are examined and examples are given. The aim is not to teach the details of VHDL, but to give an overall appreciation of its capabilities and how they compare to those of Verilog.

Example Directory

Software downloads and files for use in Tutorial Examples.

Note
To download a file :-

(1) Using Windows Explorer
Right click on required file and then choose "Save Target As..."

(2) Using Netscape Navigator
Right click on required file and then choose "Save Link As..."

Background notes for ISLI Hardware Primer module

During a lot of trawls though the web I have found a number of documents that may be of interest to you. I did not write any of them, but most have the author's names attached. If not, my apologies to the anonymous folk who wrote them.

I would say that all this information is like anything else to be found on the web, probably out of date and to be treated with caution. However, it's often worth a quick look.

DON'T just print this lot out!! Think of the trees! Read first, then, perhaps, print out the bits you really find helpful.

Assignments

Submitting Assignments to your Tutors to be Marked
The preferred method for sending assignments to your tutor is by email. You must send one copy to your tutor and copy the email to gillian.nagle@sli-institute.ac.uk so that Gillian has a back-up copy.

If you have a problem meeting an assignment deadline, contact your tutor before the deadline and ask for an extension on the date.
Your assignments are very important as they go towards your final mark for the module. If you do not have an agreed extension for submitting your assignments, your mark will be reduced at 5% a day for a late submission.

Assignment 1

This is the first Tutor Marked Assignment for this module.
It covers Units 2, 3 and 4 of the module and accounts for 20% of the overall mark.

Assignment 2

This is the second Tutor Marked Assignment for this module.
It covers Unit 5 of the module and accounts for 20% of the overall mark.