Algotronix (2005-09)

Title: Novel technologies for the protection of design information sold as ‘IP cores' for FPGA chips
Research Engineer: Carol Marsh
Sponsor: Tom Kean, Algotronix
Academic Supervision: TBC

The technologies will allow the IP core owner to adopt and enforce flexible business models beyond the traditional one time up-front fee for unlimited use of the IP Core. Alternative models include ‘pay per configured chip' in which the user is charged according to the number of FPGAs which are programmed with the IP Core – making it economic to use bought-in IP cores on small volume projects. ‘Pay per configured chip' pricing models can also be applied to CAD software, allowing the cost effective provision of advanced tools for use on lower volume projects.

The ability to enforce new licensing models such as ‘pay per configured chip' for both IP cores and software tools will be essential if FPGA technology is to be used in reconfigurable computing applications. It is not reasonable to expect a user creating a ‘program' to run on a single FPGA based computer to pay the same prices for CAD software and IP cores as an ASIC designer designing a product that will sell in high volume. Equally, IP core and software vendors will not offer their products at lower cost to the reconfigurable computing market if this threatens their ability to enforce higher pricing in the ASIC market.

The project will investigate cryptographic technologies for enforcing IP licenses and also technologies for detecting products which incorporate unlicensed IP. The project will also investigate the potential size of the market for such technologies.