ARM (2004-08)

Title: VDSM effects on on-chip communication
Research Engineer: Rahman Hassan
Sponsor: ARM
Academic Supervision: Prof Nigel Topham and Dr Aris Efthymiou,
University of Edinburgh

As process geometries shrink, the number of transistors available for designs is increasing. Hence, SoC designs are becoming ever larger, more complex and more diverse, with systems ranging from uniprocessor to distributed heterogeneous multiprocessor topologies. Furthermore, with these shrinking process geometries, conventional synchronous bus-based interconnect becomes more difficult to implement.

The research programme will explore the likely topology and interconnect requirements of future SoC systems. This will require an analysis of likely applications as well as roadmaps for silicon technology, embedded OSs and EDA toolage. It will also include modelling reference SoC implementations in order to generate patterns of interconnect traffic that can be applied to prospective solutions.

Emerging interconnect topologies will also be reviewed and the most promising used as the basis for further investigation. Techniques such as Globally Asynchronous, Locally Synchronous (GALS) topology and Network-on-Chip (NoC) will be investigated for implementing the global interconnect.