Cadence 02 (2001-05)

Title: Analysis and design of a DSP core forming the basis of the
physical layer for an ethernet first mile system
Research Engineer: Angus Nicholson
Sponsor: Cadence
Academic Supervision: Dr John Soraghan, University of Strathclyde

The research covers the analysis and design of a DSP core that will form the basis of the physical layer for an ethernet first mile (EFM) system. EFM is a technology to bring high speed Ethernet access directly to the home over the existing copper network. The problems of broadband access over copper are non-trivial due to severe inter-symbol interference associated with copper cabling.

The DSP core will be modeled in Matlab. The model developed will be used to justify the trade-off between complexity and throughput. These models will also be used to generate test vectors for the DSP core. The DSP core will be realised in Verilog and tested upon an emulation board.

The DSP core must be able to perform:

• Echo cancellation
• Removal of inter-symbol interference (ISI)
• T-spaced timing recovery
• Baseline wander control
• Scrambling

The following issues will also be investigated:

• Use of error correction (maximum entropy vs. syndrome based) to increase throughput - viz. 155 Mb Ethernet over copper.
• Use of PAM-5 (a two bit per symbol system) with a view to modifying the core to handle 1000Base-T Ethernet [1].

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