Codeplay Software Ltd. (2007-11)

Title: Automatic parallelization of C++ applications using FPGAs
Research Engineer: Haitham Fattah
Sponsor: Codeplay Software Ltd., Edinburgh
Academic Supervision: Dr Wim Vanderbauwhede, University of Glasgow
Industrial Supervision: Andrew Richards

Codeplay's Sieve system is a suite of development tools for automatic parallelization of C++ applications to run on multi-core processors. The key philosophy behind Sieve is ease of programming – a high level abstraction of parallelism avoids problems with race conditions and non-determinism, and promotes portability of code. In order to quickly target new architectures, the Sieve system provides the option of compiling parallel C++ applications to ANSI C, which can then be processed by a compliant C compiler for a given architecture.

Field programmable gate arrays (FPGAs) potentially promise high levels of computing performance with a low level of associated power consumption. However, they can be difficult to program.

The aim of the proposed project is to ease the task of programming FPGAs. This will involve researching novel compilation techniques to allow the Sieve system to work with FPGA-based accelerator cards and with the “Maxwell” FPGA supercomputer (developed by the Edinburgh Parallel Computing Centre and the FPGA High Performance Computing Alliance).

The Xilinx CHiMPS tool set currently compiles a subset of ANSI C programs to FPGAs, so it will be sufficient to extend the Sieve system to compile to this subset of C. The major research challenges are in designing new optimization techniques to output efficient C code in the context of FPGAs, and in developing a runtime system to handle data transfer and communication between FPGAs and a host machine.

In summary, the milestones of the the project are to:

• Research and develop techniques for generation of optimized C code for further processing by CHiMPS
• Design and implement a Sieve-FPGA linker and runtime system
• Work on debugging and profiling technology for the system
• Empirically evaluate the performance of the system running a selection of parallel algorithms on the Maxwell supercomputer, and on FPGA-accelerated PCs
• Assess the “ease of programming” aim of the Sieve system for FPGAs via a user evaluation

The contribution of this research to the HPC community will be a tool set which allows developers to effectively and rapidly exploit FPGA technology, using high-level programming techniques