Silistix (2007-11)

Title: GALS network-on-chip architecture
Research Engineer: Sean Salisbury
Sponsor: Silistix, Manchester
Academic Supervision: Dr Aris Efthymiou, University of Edinburgh
Industrial Supervision: John Bainbridge, Silistix

Silistix is the leader in distributed asynchronous alternatives to the conventional clocked System-on-Chip bus. The application of networking techniques to this exciting new space (known as Network-on-Chip, or NoC) is still in its infancy, and presents the potential to enable new systems not possible with current interconnect architectures through improved connectivity, reduced power consumption and area savings.

There are many issues involved in building an NoC that are yet to be resolved, including: synchronization/clocking techniques, data encodings, topology and serialisation tradeoffs, quality of service mechanisms, fault tolerance and adaptive routing to name a few.
Furthermore, the best combination of features is application specific.

This research will explore new techniques applicable to a mixed synchronous/self-timed NoC, and evaluate some of these tradeoffs.