Thales 01 (2002-06)

Title: Development of an automated route to FPGA programming
from a suite of image processing algorithms
Research Engineer: Oliver Sims
Sponsor: Thales Optronics
Academic Supervision: James Irvine, University of Strathclyde

High performance, real-time image processing is an increasing feature of imaging sensor systems within a wide range of market sectors. Thales Optronics, active in the defence market, uses these 'intelligent sensors' as a central feature of its products. The additional constraints of small size, low power, robustness and reliability drive the implementation of such processing to highly integrated devices, such as ASICs and more recently FPGAs.

ASICs provide the ultimate in integration for high speed, complex applications, however set-up costs are high. Increasingly, the industry is turning to FPGAs, where set-up costs are lower, enabling smaller quantity applications to be considered. FPGAs do offer a further benefit in their ability to be re-programmed, enabling the entire operational role of a sensor to be changed in situ, e.g., from an automatic ‘hot spot’ detection sensor to an image identification system.

The merits of FPGAs (and ASICs) are tempered by the high skill levels necessary to achieve programming of the devices. There are a number of steps to be taken to translate a series of image processing algorithms (expressed usually in a set of mathematical formulae, using a programme such as MATLAB) into the language of the FPGA device itself, which is often manufacturer-specific. This path is eased by the availability of a number of commercial tools, but these are not contiguous, leaving a considerable degree of ‘hand-crafting’ to be carried out, with the inevitable scope for error and misinterpretation. In addition, each tool brings with it additional design constraints (e.g., fixed point arithmetic instead of floating point) which may impact the effectiveness or even the viability of the original algorithm.

The initial aim of the project is to characterise and capture this design process to achieve an automated route to FPGA programming from a suite of image processing algorithms. This includes the validation of the algorithms in their final hardware state using the same test cases as were used in their original mathematical definition. Secondary aims include the definition of an appropriate hardware infrastructure within the FPGA which best supports the type of real-time image processing algorithms relevant to the application area, and which also supports dynamic reconfigurability, and selective power-down for power minimisation.

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