Xilinx 02 (2005-09)

Title: Investigation of networking applications using a high-level language and highly programmable modules

Research Engineer: Paul McKechnie
Sponsor: Xilinx
Academic Supervision: TBC

As the complexity and size of networking systems grows, the technical effort required to design such systems increases rapidly. There is an increasing need for a tool which allows high-level design entry for packet processing systems, in order to allow rapid design and redesign.

The project will investigate the use of a high-level language to describe one or more real networking applications. It will make use of a tool to produce an efficient mapping of the design to an implementation in an FPGA. The project will study techniques for automatic generation and interconnection of coarse-grained IP blocks. This will be followed by the introduction of high level descriptions of the blocks in the form of highly programmable modules. An additional area of investigation will be a study of how designs can be effectively analysed and debugged during development. The project will have the objective of producing a hardware tested implementations of the applications. The work should result in enhancements to the high level descriptions employed, improvements the effectiveness of the tool and a methodology for debugging designs within the tool environment.